The invention relates to a control circuit for use with refresh operation in a memory device. The circuit inhibits unused array blocks from refresh operation.
In dynamic random access memory (DRAM) systems, it is necessary for the information stored in the memory cells to be refreshed at cyclical intervals. In DRAM memory cells the information is stored as capacitor charges and the capacitors loose charges due to leakage currents. Consequently, the storage charges of the capacitors have to be repeatedly renewed, or the stored charge, and thus stored data, will be lost.
For all types of DRAM refresh operation is necessary to retain stored data. For synchronous dynamic random access memory (SDRAM) or double data rate synchronous dynamic random access memory (DDR SDRAM) an auto refresh or self-refresh signal is used. For example, for a 256M SDRAM or DDR SDRAM a distributed refresh command (auto refresh) is provided every 7.81 microseconds. Alternatively, 8,192 refresh commands are provided in a burst every 64 milliseconds (self refresh) in order to maintain the stored data.
The DRAM consists of a multitude of memory cells accessible by column and row. The memory cells are typically further divided into memory banks, each containing memory cell array blocks. The refreshing of memory contents of the memory cells in the DRAM is generally carried out row-by-row with an internal refresh drive circuit. For low power or mobile DRAM applications where small current consumption is emphasized to enlarge battery life, various techniques are utilized in an attempt to minimize these refresh operations, because they consume significant current. One such technique is partial array self refresh (PASR). In order to save current, this feature allows a user to select the amount of memory that will be refreshed during a self-refresh cycle. In a 256M low powered DRAM, PASR comprises each of the memory banks, two banks, one bank, a half bank, and one quarter bank. Reducing the number of banks to be refreshed saves the amount of refresh current used. Similarly, decreasing the number of refresh cycles also saves refresh current. Another technique used to save current is the deep power down mode. In order to achieve maximum current reduction, all internal voltage generators are stopped with this mode. Data will not be retained once the device enters the deep power down mode.
Although these methods save current consumption and can enlarge battery life, refreshing each row of the DRAM still consumes significant amounts of current. An improvement to refresh operation of the DRAM in order to save current would be a useful improvement to the art.